1. Field of the Invention
The invention relates to a data extracting apparatus for extracting various data inserted in a vertical blanking interval.
2. Description of the Related Art
A signal for a character broadcasting and an ID signal and the like of video addition information such as an aspect ratio and the like have been inserted in the V blanking interval of a television signal. By decoding those signals, the user can accept various services. As for those data inserted in the V blanking interval, the inserted line numbers differ in accordance with their kinds. In order to decode the data corresponding to each service, the user must prepare a number of decoders corresponding to the kinds of services.
To solve such a problem, a general decoder is known. The general decoder can decode various data inserted in lines of different V blanking intervals. FIGS. 1A and 1B show waveform diagrams of the V blanking interval and a waveform diagram of a lock flag. Data A is inserted in the V blanking interval of a television signal as shown in FIG. 1A. Data A is stored in a memory in the decoder. When the V blanking interval is finished, the decoded data is read out and a predetermined process is executed by a controller. In case of storing the data into a memory, if a PLL circuit is not locked, data A cannot be correctly sampled. Therefore, in order to confirm a locking state of the PLL circuit, the decoder refers to a lock flag. A waveform of the lock flag is shown in FIG. 1B. The lock flag is a flag indicating whether the sampling clock formed by the PLL circuit is correct or not. In this instance, it is assumed that the lock flag simply indicates the present locking state of the PLL circuit. When the PLL circuit is locked, its level is set to the H level. When the PLL circuit is not locked, the level is set to the L level.
The actual data process is executed after the end of the V blanking interval. The lock flag is referred to after the V blanking interval. Therefore, the locking state of the PLL at a time point when the lock flag is referred to is merely known and the locking state in the V blanking interval cannot be known. For example, in FIG. 1A, in the case where the PLL circuit is in an unlocked state when the data A is sampled and the PLL circuit enters a locking state before the lock flag is referred to, a data process is executed in spite of the fact that the data A is not correctly sampled.